1. Field
This disclosure relates generally to integrated circuits, and more specifically, to an integrated circuit with a programmable delay and a method thereof.
2. Related Art
Typically, an integrated circuit may have several circuit blocks that may communicate with each other synchronously. Some circuit blocks may require a constant power, whereas other circuit blocks could function at a lower power and thus reduce overall power consumption associated with the integrated circuit. Thus, the integrated circuit may be architected, such that a group of circuit blocks have a constant voltage and another group of circuit blocks can operate at a reduced or a higher voltage using dynamic voltage and frequency scaling (DVFS) techniques, for example. When a circuit block that supports DVFS communicates with a circuit block that does not support DVFS, a large clock skew may develop across the interface between the two blocks. This large clock skew may result in the violation of setup and hold time requirements associated with sequential elements of the circuit blocks. In addition to clock skew, data path delay shifts due to DVFS may exacerbate the potential for hold time failures for timing paths which cross blocks.
Additionally, when all of the circuit blocks of an integrated circuit are operated at a reduced voltage or a higher voltage increased clock skews can be introduced. Accordingly, there is a need for an integrated circuit with programmable delay and a method thereof.